Embodiments of the present invention relate to the radio frequency (RF) receivers, and more particularly, to RF mixers.
Mixers used in receivers today typically down-convert signals from various harmonics of a local oscillator frequency (LO) due to the square wave LO used in these implementations. Although the square wave LO results in better noise and linearity compared to a sinusoidal LO, the RF signal at harmonics of the square wave alias into the desired signal band at the output of the mixer. This is a major problem in broad-band systems such as TV tuners or cable-systems, where the input signal range is wide-band.
Harmonic reject mixers have been developed to eliminate the signal down-converted from higher harmonics. They achieve this by using multiple mixing blocks (alternatively referred to and shown herein as a switch) as shown in FIG. 1. Each switch 10 of FIG. 1 is clocked with a different phase of the LO. The mixing block outputs are weighted and summed so as to create an effective LO mixing waveform that is more sinusoidal than square. The harmonics of the RF signal that are rejected depend on the number of mixing blocks, or number of “samples of the RF output”. For example a 2N-tap harmonic rejection topology, realized using N differential mixing blocks, eliminates all harmonics except those at (m*2N)−1 and (m*2N)+1, where m is an integer. Implementation of the 2N tap harmonic reject mixer 20 is shown in FIG. 1. The LO waveforms shown in FIG. 1 are for N=8. This is a specific example of harmonic rejection topology where cancellation of harmonics is done in the base-band after summation of various base-band taps. The base-band outputs are summed with the corresponding weighting factors to generate quadrature signals.
FIG. 2 is a block diagram of a harmonic reject mixer 20 for which N=4, as known in the prior art. Harmonic reject mixer 20 eliminates 3rd and 5th harmonics of the RF signal. Harmonic reject mixer 20 is shown as including eight switches 10. The output signals of the base-band amplifiers 12 are converted to currents by resistors 14 whose resistances represent weights or coefficients applied to the output signals of amplifiers 12. The output currents of resistors 14 are subsequently summed by amplifiers 16. As shown, weighted phases 0, 45 and 90 are added by adder 16 to generate the In-phase OUT_I component of the output signal, and weighted phases 45, 90 and 135 are added by adder 18 to generate the quadrature-phase OUT_Q component of the output signal.
In conventional reject mixers each sample of the received RF signal is defined by a separate switch and is hence susceptible to phase and duty cycle mismatches in the switches or the LO path. Phase and gain errors through the different taps limit the ultimate rejection achievable from the topology. Imperfections in the LO generation and mixing blocks result in a phase offset and duty cycle error. Phase errors result in imperfect cancellation of harmonics at the summing node. Duty cycle errors result in amplitude mismatch that also limits the harmonic rejection.
Impact of gain errors can be minimized by using a conventional dual harmonic reject architecture. In such an architecture, outputs of multiple number of harmonic reject mixers that are phase shifted with respect to one another are weighted and combined to get the second layer of harmonic rejection. Minimizing phase and duty cycle errors without taking care of gain errors or vice versa limits the improvement in harmonic rejection that can be achieved.
Accordingly, it would be beneficial to provide a harmonic rejection mixer with reduced sensitivity to gain and phase mismatches.